The concept of resistance interval: a new parametric model for realistic resistive bridging fault

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	Similar Articles Articles by M. Renovell Articles by P. Huc Articles by Y. Bertrand

13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	M. Renovell, P. Huc, Y. Bertrand, "The concept of resistance interval: a new parametric model for realistic resistive bridging fault," VLSI Test Symposium, IEEE, pp. 0184, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512635, author = {M. Renovell and P. Huc and Y. Bertrand}, title = {The concept of resistance interval: a new parametric model for realistic resistive bridging fault}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0184}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512635}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - The concept of resistance interval: a new parametric model for realistic resistive bridging fault SN - 0-8186-7000-2 SP EP A1 - M. Renovell, A1 - P. Huc, A1 - Y. Bertrand, PY - 1995 KW - VLSI; integrated circuit testing; fault diagnosis; logic testing; logic gates; automatic testing; electric resistance; resistance interval; parametric model; resistive bridging fault; intrinsic resistance; logic behavior; bridging faults; faulty behavior; fault detection; fault coverage; VLSI; logic gates; 0 to 500 ohm VL - 0 JA - VLSI Test Symposium, IEEE ER -

M. Renovell, Lab. d'Informatique, Robotique et Microelectronique, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

P. Huc, Lab. d'Informatique, Robotique et Microelectronique, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Y. Bertrand, Lab. d'Informatique, Robotique et Microelectronique, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512635

Abstract: From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 /spl Omega/ to 500 /spl Omega/. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible, do not accurately and realistically represent the behavior of the fault. Third, a new parametric bridging fault model is proposed allowing to realistically represent the faulty behavior according to the intrinsic resistance which is not known a priori. Finally, a parametric bridging fault simulation algorithm is described together with some redefinition of the classical concepts of fault detection and fault coverage.

Index Terms:

VLSI; integrated circuit testing; fault diagnosis; logic testing; logic gates; automatic testing; electric resistance; resistance interval; parametric model; resistive bridging fault; intrinsic resistance; logic behavior; bridging faults; faulty behavior; fault detection; fault coverage; VLSI; logic gates; 0 to 500 ohm

Citation:

M. Renovell, P. Huc, Y. Bertrand, "The concept of resistance interval: a new parametric model for realistic resistive bridging fault," vts, pp.0184, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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