Iddt testing of continuous-time filters

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	Similar Articles Articles by J. Arguelles Articles by M.J. Lopez Articles by J. Blanco Articles by M. Martinez Articles by S. Bracho

13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	J. Arguelles, M.J. Lopez, J. Blanco, M. Martinez, S. Bracho, "Iddt testing of continuous-time filters," VLSI Test Symposium, IEEE, pp. 0101, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512624, author = {J. Arguelles and M.J. Lopez and J. Blanco and M. Martinez and S. Bracho}, title = {Iddt testing of continuous-time filters}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0101}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512624}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Iddt testing of continuous-time filters SN - 0-8186-7000-2 SP EP A1 - J. Arguelles, A1 - M.J. Lopez, A1 - J. Blanco, A1 - M. Martinez, A1 - S. Bracho, PY - 1995 KW - continuous time filters; integrated circuit testing; design for testability; built-in self test; automatic testing; CMOS analogue integrated circuits; continuous-time filters; design-for-test methodology; dynamic supply current consumption; built-in current sensor; dynamic current; partitioning methodology; test reliability; automatic test equipment; CMOS VL - 0 JA - VLSI Test Symposium, IEEE ER -

J. Arguelles, Dept. de Electron., Cantabria Univ., Santander, Spain

M.J. Lopez, Dept. de Electron., Cantabria Univ., Santander, Spain

J. Blanco, Dept. de Electron., Cantabria Univ., Santander, Spain

M. Martinez, Dept. de Electron., Cantabria Univ., Santander, Spain

S. Bracho, Dept. de Electron., Cantabria Univ., Santander, Spain

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512624

Abstract: A Design-for-Test (DfT) methodology is proposed to perform an analysis of the dynamic supply current consumption as a testing methodology for continuous time filters. A built-in current sensor has been developed to analyze the dynamic current and a partitioning methodology, based on this sensor, has been developed to improve test reliability on large circuits under test. The DfT proposal allows one to use a conventional digital automatic test equipment (ATE) on this analog circuit type. Some experimental results are reported to illustrate the proposed DfT method.

Index Terms:

continuous time filters; integrated circuit testing; design for testability; built-in self test; automatic testing; CMOS analogue integrated circuits; continuous-time filters; design-for-test methodology; dynamic supply current consumption; built-in current sensor; dynamic current; partitioning methodology; test reliability; automatic test equipment; CMOS

Citation:

J. Arguelles, M.J. Lopez, J. Blanco, M. Martinez, S. Bracho, "Iddt testing of continuous-time filters," vts, pp.0101, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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