13th IEEE VLSI Test Symposium (VTS'95)
An approach to dynamic power consumption current testing of CMOS ICs
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
J.A. Segura, Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
M. Roca, Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
D. Mateo, Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
A. Rubio, Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
Abstract: I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.
Index Terms:
integrated circuit testing; CMOS logic circuits; fault diagnosis; logic testing; electric current measurement; adders; automatic testing; dynamic power consumption current testing; CMOS ICs; I/sub DDQ/ testing; logic behavior; bridging defects; parametric defect; open defects; quiescent power supply current testing; consumption current testing time; transient current; on-chip sensor; static power consumption; full adders
Citation:
J.A. Segura, M. Roca, D. Mateo, A. Rubio, "An approach to dynamic power consumption current testing of CMOS ICs," vts, pp.0095, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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