13th IEEE VLSI Test Symposium (VTS'95)
On the decline of testing efficiency as fault coverage approaches 100%
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
Abstract: Testing is an indispensable process to weed out the defective parts coming out of the manufacturing process. Traditionally, test generation targets on a specific fault model, usually the single stuck-at fault model, to produce tests that are expected to identify defects such as unintended shorts and opens. With this approach, the test quality relies on fortuitous detection of the non-target defects. As the quality demands and circuit sizes increase, the feasibility of test generation on a single fault model becomes questionable. In the paper, we present empirical data from experiments on ISCAS benchmark circuits to demonstrate that using traditional methods the probability of detecting nontarget defects drops rapidly as the fault coverage approaches 100%. By assuming surrogates, we explain the mechanism which produces this effect and describe a new test pattern generation approach with better testing efficiency.
Index Terms:
fault diagnosis; logic testing; automatic testing; integrated circuit testing; production testing; testing efficiency; fault coverage; manufacturing process; single stuck-at fault model; test quality; circuit sizes; ISCAS benchmark circuits; nontarget defects; test pattern generation
Citation:
L.-C. Wang, P.R. Mercer, S.W. Kao, T.W. Williams, "On the decline of testing efficiency as fault coverage approaches 100%," vts, pp.0074, 13th IEEE VLSI Test Symposium (VTS'95), 1995