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13th IEEE VLSI Test Symposium (VTS'95)
Verification of transient response of linear analog circuits
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
A. Balivada, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Y. Hoskote, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Abstract: With the introduction of complex analog designs the need to verify the circuit behavior completely and efficiently cannot be overemphasized. Recognizing the limitation of circuit simulation to achieve this goal, we present a novel approach based on formal techniques developed for digital circuits. Given a transfer function (specification) and its implementation using operational amplifier macro circuits, we verify the correctness of the transient behavior of the implementation over all possible input waveforms. Transforming the specification and the extracted state equations of the implementation from the s-domain to the Z-domain facilitates a digital representation in terms of adders, multipliers and delay elements. These two digitized circuits are then compared using techniques for checking compatibility of states in finite state machines. An example that illustrates the technique is presented.
Index Terms:
transient response; transient analysis; linear network analysis; transfer functions; operational amplifiers; active networks; frequency-domain analysis; equivalent circuits; analogue circuits; state-space methods; transient response; linear analog circuits; circuit behavior; formal techniques; transfer function; operational amplifier macro circuits; input waveforms; extracted state equations; Z-domain; finite state machines; digital representation
Citation:
A. Balivada, Y. Hoskote, J.A. Abraham, "Verification of transient response of linear analog circuits," vts, pp.0042, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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