An approach is presented for identifying structural-faults, using the charge-frequency based built-in-self test (CF-BIST) technique in a phase-locked loop (PLL) circuit, for a standard 0.18 µm CMOS process. This method not only validated the CF-BIST approach for fault detection, but also showed an algorithm for how this approach may possibly be used for fault diagnosis as well, for a wide frequency PLL. The method of fault diagnosis is based on measuring the 8-bit digital values from the voltage-controlled oscillator (VCO)/Divide-by-N counter and performing comparisons between the values for the fault-free and fault-introduced conditions.