A novel asymmetric skewed buffer is proposed to reduce the subthreshold leakage of standard CMOS non-inverting buffers. Using oppositely skewed inverters to drive the NMOS and PMOS of the second inverter creates a small time window during which both transistors are conducting, enhancing speed. Given this performance advantage over traditional CMOS buffers, the leakage current can then be suppressed by either downsizing transistors or by assigning high-Vt devices. Based on simulation results for a 0.13 ?m technology, leakage is reduced by up to 4.4 times when the input is high while maintaining fixed dynamic power dissipation and propagation delay compared to CMOS.