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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
An Operational Amplifier Model for Test Planning at Behavioral Level
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
ASCII Text
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Eduardo Romero, Gabriela Peretti, Carlos Marqu?, "An Operational Amplifier Model for Test Planning at Behavioral Level," VLSI Design, International Conference on, pp. 812-815, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.
 
 
BibTex
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@article{ 10.1109/ICVD.2005.51,
author = {Eduardo Romero and Gabriela Peretti and Carlos Marqu?},
title = {An Operational Amplifier Model for Test Planning at Behavioral Level},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2005},
issn = {1063-9667},
pages = {812-815},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.51},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - An Operational Amplifier Model for Test Planning at Behavioral Level
SN - 1063-9667
SP812
EP815
A1 - Eduardo Romero,
A1 - Gabriela Peretti,
A1 - Carlos Marqu?,
PY - 2005
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Eduardo Romero, National University of Technology
Gabriela Peretti, National University of Technology
Carlos Marqu?, National University of C?rdoba
A new Operational Amplifier model for evaluating test strategies at behavioral level is proposed. It presents a set of very appealing characteristics for behavioral-level fault injection and simulation. The matching between behavioral-level model and transistor-level one is evaluated in order to validate the model. A second hypothetical OPA is modeled, for illustrating the use of the model in the evaluation of a test strategy at behavioral level.
Citation:
Eduardo Romero, Gabriela Peretti, Carlos Marqu?, "An Operational Amplifier Model for Test Planning at Behavioral Level," vlsid, pp.812-815, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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