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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
ASCII Text
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Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta, "Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications," VLSI Design, International Conference on, pp. 780-783, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.
 
 
BibTex
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@article{ 10.1109/ICVD.2005.102,
author = {Saurabh Kumar Singh and T. K. Bhattacharyya and Ashudeb Dutta},
title = {Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2005},
issn = {1063-9667},
pages = {780-783},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.102},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Design, International Conference on
TI - Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications
SN - 1063-9667
SP780
EP783
A1 - Saurabh Kumar Singh,
A1 - T. K. Bhattacharyya,
A1 - Ashudeb Dutta,
PY - 2005
KW - Analog integrated circuits
KW - CMOS RF
KW - Frequency synthesizer
KW - Phase locked loop
KW - ZigBee
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Saurabh Kumar Singh, Indian Institute of Technology-Kharagpur
T. K. Bhattacharyya, Indian Institute of Technology-Kharagpur
Ashudeb Dutta, Indian Institute of Technology-Kharagpur
A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18? CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling time is 300?sec. Synthesizer consumes 22mW of power at supply voltage of 1.8V and occupies an active area of mm².
Index Terms:
Analog integrated circuits, CMOS RF, Frequency synthesizer, Phase locked loop, ZigBee
Citation:
Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta, "Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications," vlsid, pp.780-783, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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