Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucial to the performance and reliability of SoC designs. This paper presents a new on-chip bus encoding scheme targeting high performance generic SoC systems. In addition to its efficiency in terms of power, the scheme reduces delay faults by completely eliminating the most critical type of crosstalk coupling that causes three adjacent wires to undergo Miller-like transition simultaneously. The paper describes the technique, its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provides results indicating between 24% to 38% energy saving for systems implemented in 0.18?m CMOS technology.