Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs

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	Similar Articles Articles by Saurabh Goyal Articles by Mihir Choudhury Articles by S. S. S. P. Rao Articles by Kalyan Kumar

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)

Kolkata, India

January 03-January 07

ISBN: 0-7695-2264-5

	ASCII Text	x
	Saurabh Goyal, Mihir Choudhury, S. S. S. P. Rao, Kalyan Kumar, "Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs," VLSI Design, International Conference on, pp. 742-747, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.122, author = {Saurabh Goyal and Mihir Choudhury and S. S. S. P. Rao and Kalyan Kumar}, title = {Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {742-747}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.122}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs SN - 1063-9667 SP742 EP747 A1 - Saurabh Goyal, A1 - Mihir Choudhury, A1 - S. S. S. P. Rao, A1 - Kalyan Kumar, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Saurabh Goyal, Indian Institute of Technology-Bombay

Mihir Choudhury, Indian Institute of Technology-Bombay

S. S. S. P. Rao, Indian Institute of Technology-Bombay

Kalyan Kumar, Intel Technology India Pvt. Ltd.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.122

We shall present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops has also been proposed. The aim is to integrate testing of LUTs, flip flops and multiplexers which will reduce the number of configurations and hence minimize the testing time.

Citation:

Saurabh Goyal, Mihir Choudhury, S. S. S. P. Rao, Kalyan Kumar, "Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs," vlsid, pp.742-747, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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