We propose a novel single event fault/error model based on Logic Induced Fault Encoded Directed Acyclic Graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in nano-domain logic block) that depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, we show that we are able to estimate detection probabilities of single-event faults/errors on ISCAS?85 benchmarks with high accuracy (zero-error), linear space requirement complexity, and with an order of magnitude (≈ 5 times) reduction in estimation time over corresponding BDD based approaches.