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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
The Impact of Inductance on Transients Affecting Gate Oxide Reliability
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
N. S. Nagaraj, Texas Instruments Inc.
William R Hunter, Texas Instruments Inc.
Poras Balsara, University of Texas at Dallas
Cyrus Cantrell, University of Texas at Dallas
Ringing due to inductance has an increased significance on Gate Oxide Reliability (GOR), as failure rate is exponentially dependent on the effective voltage stress. Unlike lumped capacitance (C), self-inductance (L) itself has an impact on GOR failure rate. An added complexity in parasitic inductance extraction is that the inductance matrix is much larger than the capacitance matrix, as mutual inductance terms (K) decay slowly with distance. A comparative modeling study of the dependence of GOR failure rate on RC, RCL and RCLK effects is presented. A key finding from this study is that mutual inductance has a very large impact on GOR failure rate and needs accurate modeling. Methods to minimize GOR failure rate increases caused by parasitic inductance are discussed. This embedded tutorial covers the theory of Gate Oxide Reliability, mathematical approximations for estimating failure rates, theory of inductance modeling and a detailed study of the impact of inductance on GOR.
Citation:
N. S. Nagaraj, William R Hunter, Poras Balsara, Cyrus Cantrell, "The Impact of Inductance on Transients Affecting Gate Oxide Reliability," vlsid, pp.709-713, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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