Accurate estimation of energy dissipation and thermal effects in buses is essential to correctly predicting reliability and performance characteristics and packaging requirements of ICs. As fabrication technologies scale down and low-K inter-metal and inter-layer dielectrics are introduced to reduce RC delay, dynamic power dissipation, and crosstalk, study of thermal effects, particularly for global signal buses that switch at high clock frequencies, are becoming more and more important. Further, power dissipation and hence temperature rise and reliability of bus lines are time- and information-dependent, which makes dynamic simulation studies necessary. This paper presents a bus energy dissipation and thermal model that enables designers to simultaneously study energy and thermal effects in global signal buses using real-world address traces. Using this model, the energy dissipation and temperature rise in 32-bit instruction and data address buses are studied with traces obtained from SPEC CPU2000 benchmark programs.