Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores

V
VLSID
2005
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
Abstract - Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by C. H. Wang Articles by A. T. Erdogan Articles by T. Arslan

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)

Kolkata, India

January 03-January 07

ISBN: 0-7695-2264-5

	ASCII Text	x
	C. H. Wang, A. T. Erdogan, T. Arslan, "Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores," VLSI Design, International Conference on, pp. 659-662, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.44, author = {C. H. Wang and A. T. Erdogan and T. Arslan}, title = {Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {659-662}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.44}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores SN - 1063-9667 SP659 EP662 A1 - C. H. Wang, A1 - A. T. Erdogan, A1 - T. Arslan, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

C. H. Wang, University of Edinburgh

A. T. Erdogan, University of Edinburgh and Institute of System Level Integration, The ALBA campus

T. Arslan, University of Edinburgh and Institute of System Level Integration, The ALBA campus

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.44

This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilization of algorithms such as coefficient segmentation, block processing and combined segmentation and block processing algorithms. On the other hand, multiple data paths are utilized for achieving high performance. The paper presents the complete architectural implementation of these algorithms for high performance applications. The paper describes the design methodology, evaluation environment, and provides results which show up to 40% reduction in power consumption.

Citation:

C. H. Wang, A. T. Erdogan, T. Arslan, "Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores," vlsid, pp.659-662, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.