Vertical integration of active device layers in the third dimension makes room for significant reduction in interconnect lengths leading to decrease in both delay and power consumption associated with interconnects. This characteristic can be well leveraged only by judicious layer assignment of active devices. To address layer assignment as a part of behavioral synthesis, we proposed a 0-1 linear program formulation to simultaneously schedule, bind and perform layer assignment for synthesis of vertically integrated 3D systems. In these systems, inter-stratal communication occurs through inter-layer vias that have higher resistivity and capacitance. In this paper, we propose a trade-off between reducing the total interconnect delay in critical paths while reducing the inter-stratal communication. Three different objective models are proposed and their combinations examined to find the most suitable methodology to achieve these goals. A power gradient is proposed between layers to address the thermal issues associated with these systems that has been shown to be of concern. Results show a significant reduction in total interconnect lengths compared to a traditional two-dimensional implementation. The examination of the various proposed optimization objectives indicate that a combination of communication minimization and critical path optimization leads to the best synthesis results for a range of benchmarks.