With the increasing operating frequencies and functionality in modern VLSI designs, the resulting size of circuit equations of high-frequency modules are becoming large. Two-level passive model-reduction bared algorithms were recently suggested to obtain compact macromodels for fast transient analysis of large scale VLSI circuits and interconnect networks. However, one of the major issues involved with current second level reduction algorithms is the high computation expense. In order to overcome this difficulty, this paper describes an efficient algorithm for reducing the computational cost involved in second level passive reduction algorithms. Necessary formulation and validation examples are given.