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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
ASCII Text
x 
 
P. Kalpana, K. Gunavathi, "A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets," VLSI Design, International Conference on, pp. 504-507, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.2005.28,
author = {P. Kalpana and K. Gunavathi},
title = {A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2005},
issn = {1063-9667},
pages = {504-507},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.28},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets
SN - 1063-9667
SP504
EP507
A1 - P. Kalpana,
A1 - K. Gunavathi,
PY - 2005
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
P. Kalpana, PSG College of Technolgy
K. Gunavathi, PSG College of Technolgy
For analog and mixed signal circuits, the traditional tests are time consuming and also most expensive in terms of both test development and test implementation costs .So for testing these ICs new testing strategies are investigated. In this paper, a novel test generation methodology for the detection of faults in analog cores is proposed. A transient signal is taken as input stimulus for the circuit under test and the output response is analysed using wavelets. Specifications of the circuit are mapped to the performance space and the specifications are checked implicitly. The proposed fault oriented test generator also computes the optimal test patterns based on genetic algorithm.
Citation:
P. Kalpana, K. Gunavathi, "A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets," vlsid, pp.504-507, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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