Visualization of circuits is an important research area in electronic design automation. Locating errors in a large design may require a high-quality graphical representation of a circuit that allows humans to understand it. Usually, drawing a circuit is based on visualizing the corresponding graph or hypergraph structure where nodes are connected by straight lines, and nodes are located in a way that minimizes the crossings of these lines. Then the algorithms re-transform this graph representation back to an orthogonal circuit structure, i.e. it replaces the straight lines by horizontal and vertical lines.

In contrast to many other approaches which route all the wiring after placing all nodes we focus on a new approach which dynamically reorders the nodes within the layers to further reduce the number of hyperedge crossings. An efficient algorithm is presented that minimizes the hyperedge crossings. Experimental results are provided which show that the drawings can be improved significantly while the run time remains moderate.