18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05) Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes Kolkata, India January 03-January 07 ISBN: 0-7695-2264-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.65
A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent cross-talk and provide error correction. In this paper, we present fundamental limits on the number of wires required to achieve joint crosstalk avoidance and error correction in on-chip buses. We propose a code construction that results in practical encoding and decoding schemes with the number of wires being within 35% of the fundamental limits. The proposed codes, when applied to a 10-mm 32-bit bus in a 0.13-?m CMOS technology with low-swing signaling, provide 2.14? speed-up and 27.5% energy savings without any loss in reliability.
Citation:
Srinivasa R. Sridhara, Naresh R. Shanbhag, "Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes," vlsid, pp.417-422, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||