The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over the chip area can no longer be ignored during design.

This paper presents a novel technique where selective replacement of gates at the intersection of hotspots and critical path is carried out. This can result in area gain for a specific performance constraint or performance gain for a specific area constraint. The technique has been formulated, implemented using a proposed flow based on our own converters integrated with commercial tools and tested. The results show more than 10% area reduction over the designs using the current practice of worst-case temperature implementations.