18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05) Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty Kolkata, India January 03-January 07 ISBN: 0-7695-2264-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.111
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V_dd/V_th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.
Citation:
Yuh-Fang Tsai, N. Vijaykrishnan, Yuan Xie, Mary Jane Irwin, "Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty," vlsid, pp.374-379, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||