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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
A 160MSPS 8-Bit Pipeline Based ADC
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
ASCII Text
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Samiran Halder, Arindrajit Ghosh, Ravi sankar Prasad, Anirban Chatterjeee, Swapna Banerjee, "A 160MSPS 8-Bit Pipeline Based ADC," VLSI Design, International Conference on, pp. 313-318, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.
 
 
BibTex
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@article{ 10.1109/ICVD.2005.7,
author = {Samiran Halder and Arindrajit Ghosh and Ravi sankar Prasad and Anirban Chatterjeee and Swapna Banerjee},
title = {A 160MSPS 8-Bit Pipeline Based ADC},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2005},
issn = {1063-9667},
pages = {313-318},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.7},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A 160MSPS 8-Bit Pipeline Based ADC
SN - 1063-9667
SP313
EP318
A1 - Samiran Halder,
A1 - Arindrajit Ghosh,
A1 - Ravi sankar Prasad,
A1 - Anirban Chatterjeee,
A1 - Swapna Banerjee,
PY - 2005
KW - Double sampling Sample-and-Hold
KW - Comparator
KW - Multiplying digital-to-analog converter
KW - Pipeline architecture
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Samiran Halder, IHP- Germany
Arindrajit Ghosh, Indian Institute of Technology-Kharagpur
Ravi sankar Prasad, Indian Institute of Technology-Kharagpur
Anirban Chatterjeee, Qualcorelogic Ltd Habsiduda
Swapna Banerjee, Indian Institute of Technology-Kharagpur
This paper presents an 8-bit 160-MS/s pipeline analog-to-digital converter using 0.25-micrometer double poly BiCMOS technology of which the total power dissipation is 135mW with 3.3V of analog power supply. The input signal is assumed to be 1V. Double sampling technique is used to increase the sampling speed. The sub-circuits are optimized in terms of power and speed. It achieves differential nonlinearity and integral nonlinearity of ?0.65 LSB and ?0.8 LSB and an estimated area of 1.60mm².
Index Terms:
Double sampling Sample-and-Hold, Comparator, Multiplying digital-to-analog converter, Pipeline architecture
Citation:
Samiran Halder, Arindrajit Ghosh, Ravi sankar Prasad, Anirban Chatterjeee, Swapna Banerjee, "A 160MSPS 8-Bit Pipeline Based ADC," vlsid, pp.313-318, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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