Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder

V
VLSID
2005
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
Abstract - Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder

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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)

Kolkata, India

January 03-January 07

ISBN: 0-7695-2264-5

	ASCII Text	x
	Yuanzhong Wan, Maitham Shams, "Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder," VLSI Design, International Conference on, pp. 261-266, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.132, author = {Yuanzhong Wan and Maitham Shams}, title = {Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {261-266}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.132}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder SN - 1063-9667 SP261 EP266 A1 - Yuanzhong Wan, A1 - Maitham Shams, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Yuanzhong Wan, Carleton University

Maitham Shams, Carleton University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.132

In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. The result was then used as a guide during the design of a 64-bit high-speed static adder. Simulation results indicated a worst-case critical-path delay of 650ps for a device based on TSMC 0.18µ m technology. ..

Citation:

Yuanzhong Wan, Maitham Shams, "Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder," vlsid, pp.261-266, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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