Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder

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	Similar Articles Articles by Hafiz Md. Hasan Babu Articles by Ahsan Raja Chowdhury

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)

Kolkata, India

January 03-January 07

ISBN: 0-7695-2264-5

	ASCII Text	x
	Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury, "Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder," VLSI Design, International Conference on, pp. 255-260, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.74, author = {Hafiz Md. Hasan Babu and Ahsan Raja Chowdhury}, title = {Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {255-260}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.74}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder SN - 1063-9667 SP255 EP260 A1 - Hafiz Md. Hasan Babu, A1 - Ahsan Raja Chowdhury, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Hafiz Md. Hasan Babu, University of Dhaka

Ahsan Raja Chowdhury, University of Dhaka

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.74

In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.

Citation:

Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury, "Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder," vlsid, pp.255-260, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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