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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
Muhammad Arsalan, Carleton University
Maitham Shams, Carleton University
To get maximum energy efficiency from adiabatic logic circuits several charge-recovery power clock generators (PCGs) have been published in recent years. This paper compares and analyzes the performance and energy efficiency of various PCGs in a uniform test environment. The test benches are layed out in a standard 0.18 ?m CMOS technology and the results are mainly based on post layout simulations.
Citation:
Muhammad Arsalan, Maitham Shams, "Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits," vlsid, pp.171-174, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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