Rapid Embedded Hardware/Software System Generation

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	Similar Articles Articles by Jorgen Peddersen Articles by Seng Lin Shee Articles by Andhi Janapsatya Articles by Sri Parameswaran

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)

Kolkata, India

January 03-January 07

ISBN: 0-7695-2264-5

	ASCII Text	x
	Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran, "Rapid Embedded Hardware/Software System Generation," VLSI Design, International Conference on, pp. 111-116, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.145, author = {Jorgen Peddersen and Seng Lin Shee and Andhi Janapsatya and Sri Parameswaran}, title = {Rapid Embedded Hardware/Software System Generation}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {111-116}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.145}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Rapid Embedded Hardware/Software System Generation SN - 1063-9667 SP111 EP116 A1 - Jorgen Peddersen, A1 - Seng Lin Shee, A1 - Andhi Janapsatya, A1 - Sri Parameswaran, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Jorgen Peddersen, University of New South Wales and National Information and Communications Technology Australia

Seng Lin Shee, University of New South Wales and National Information and Communications Technology Australia

Andhi Janapsatya, University of New South Wales

Sri Parameswaran, University of New South Wales and National Information and Communications Technology Australia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.145

This paper presents an RTL generation scheme for a SimpleScalar/PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30% , energy consumed reduced by 24%, and performance improved by 24%.

Citation:

Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran, "Rapid Embedded Hardware/Software System Generation," vlsid, pp.111-116, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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