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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
Variance Reduction in Monte Carlo Capacitance Extraction
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
ASCII Text
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Shabbir H. Batterywala, Madhav P. Desai, "Variance Reduction in Monte Carlo Capacitance Extraction," VLSI Design, International Conference on, pp. 85-90, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.
 
 
BibTex
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@article{ 10.1109/ICVD.2005.169,
author = {Shabbir H. Batterywala and Madhav P. Desai},
title = {Variance Reduction in Monte Carlo Capacitance Extraction},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2005},
issn = {1063-9667},
pages = {85-90},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.169},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Variance Reduction in Monte Carlo Capacitance Extraction
SN - 1063-9667
SP85
EP90
A1 - Shabbir H. Batterywala,
A1 - Madhav P. Desai,
PY - 2005
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Shabbir H. Batterywala, Synopsys (India) Pvt. Ltd.
Madhav P. Desai, Indian Institute of Technology-Mumbai
In this article we address efficiency issues in implementation of Monte Carlo algorithm for 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation ofMonte Carlo algorithm is completely determined by the first hop in random walk. This in turn facilitates application of variance reduction techniques like importance sampling and stratified sampling to be used effectively. Experimental results indicate average speedup of 16X in simple uniform dielectric technologies, 7.3X in technologies with layers of dielectrics and 4.6X in technologies having conformal dielectrics.
Citation:
Shabbir H. Batterywala, Madhav P. Desai, "Variance Reduction in Monte Carlo Capacitance Extraction," vlsid, pp.85-90, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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