On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios

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	Similar Articles Articles by Huaxing Tang Articles by Chen Wang Articles by Janusz Rajski Articles by Sudhakar M. Reddy Articles by Jerzy Tyszer Articles by Irith Pomeranz

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)

Kolkata, India

January 03-January 07

ISBN: 0-7695-2264-5

	ASCII Text	x
	Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz, "On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios," VLSI Design, International Conference on, pp. 59-64, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.127, author = {Huaxing Tang and Chen Wang and Janusz Rajski and Sudhakar M. Reddy and Jerzy Tyszer and Irith Pomeranz}, title = {On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {59-64}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.127}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios SN - 1063-9667 SP59 EP64 A1 - Huaxing Tang, A1 - Chen Wang, A1 - Janusz Rajski, A1 - Sudhakar M. Reddy, A1 - Jerzy Tyszer, A1 - Irith Pomeranz, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Huaxing Tang, University of Iowa

Chen Wang, Mentor Graphic Corporation

Janusz Rajski, Mentor Graphic Corporation

Sudhakar M. Reddy, University of Iowa

Jerzy Tyszer, Poznan University of Technology

Irith Pomeranz, Purdue University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.127

We propose an enhanced selective compaction scheme, which integrates three techniques, called selectively filled tests, selective chains masking and selective chains observation, to reduce the impact of unknown values on the test response compaction ratio. Experimental results on several industrial designs demonstrate the effectiveness of the proposed scheme in achieving a very high test response compaction ratio without compromising the test quality.

Citation:

Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz, "On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios," vlsid, pp.59-64, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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