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17th International Conference on VLSI Design
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
ASCII Text
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Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar, "A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation," VLSI Design, International Conference on, pp. 1071, 17th International Conference on VLSI Design, 2004.
 
 
BibTex
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@article{ 10.1109/ICVD.2004.1261071,
author = {Kavish Seth and P. Rangarajan and S. Srinivasan and V. Kamakoti and V. Bala Kuteshwar},
title = {A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2004},
issn = {1063-9667},
pages = {1071},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261071},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Design, International Conference on
TI - A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation
SN - 1063-9667
SP
EP
A1 - Kavish Seth,
A1 - P. Rangarajan,
A1 - S. Srinivasan,
A1 - V. Kamakoti,
A1 - V. Bala Kuteshwar,
PY - 2004
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Kavish Seth, Atheros India LLC
P. Rangarajan, SVEC, Chennai
S. Srinivasan, IIT Madras
V. Kamakoti, IIT Madras
V. Bala Kuteshwar, Atheros India LLC
This paper describes a fully pipelined parallel architecture for the New Three Step Search (NTSS) hierarchical search block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing external memory accesses are also developed. The proposed architecture produces efficient solution for real-time motion estimation required in video applications with low memory bandwidth requirement. This architecture is the best tradeoff in terms of hardware overload and speed among the all-existing Three Step Search (TSS) architectures and is also suitable for estimation of small motion in video coding. This architecture can be used for various video applications from low bit-rate video to HDTV systems.
Citation:
Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar, "A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation," vlsid, pp.1071, 17th International Conference on VLSI Design, 2004
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