Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep submicron process technology. In this paper, we propose complete and self-consistent dynamic noise margin definitions to reduce the pessimism of conventional static noise margin based noise analysis. A simple and accurate dynamic noise margin model is then developed based on a new figure of merit, which is the ratio between the input noise duration and the sum of gate load capacitance and gate intrinsic capacitance. An efficient dynamic noise margin based noise analysis method is presented.