In this paper a new interconnect prediction based VLSI design flow is proposed. The novelty of this flow lies in the use of a unique wire length distribution called the maximum multiplicity distribution (MMD) to predict individual wire lengths in a logical netlist, which is then later used to drive the placement during physical design. In this paper, it is shown that these wire length predictions can be used to predict the capacitive loads of individual gates with an average error of 6.5%. In addition, this MMD-based length prediction driven placement (LPDP) methodology also results in an average reduction of the number of global interconnects by 32%, the length of global interconnects by 40%, and maximum length of interconnects by 15% when compared with a traditional placement that minimizes total wire length.