17th International Conference on VLSI Design
Constrained Floorplanning with Whitespace
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
This paper considers the constrained floorplanning problem in the context of a design scenario where floorplans are required to contain some white space to facilitate subsequent buffer insertion. An elegant bounded iterative methodology for floorplan-refinement based on the min-cost max-flow formulation of Feng et al [1] augmented by a heuristic area-redistribution algorithm is presented. This approach results in substantially bet-ter quality floorplans than previously reported as substantiated by our experimental results.
Citation:
Yan Feng, Dinesh Mehta, "Constrained Floorplanning with Whitespace," vlsid, pp.969, 17th International Conference on VLSI Design, 2004
Usage of this product signifies your acceptance of the
Terms of Use.
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||