Instruction-Based Delay Fault Self-Testing of Processor Cores

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Instruction-Based Delay Fault Self-Testing of Processor Cores

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Virendra Singh, Michiko Inoue, Kewal K Saluja, Hideo Fujiwara, "Instruction-Based Delay Fault Self-Testing of Processor Cores," VLSI Design, International Conference on, pp. 933, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1261051, author = {Virendra Singh and Michiko Inoue and Kewal K Saluja and Hideo Fujiwara}, title = {Instruction-Based Delay Fault Self-Testing of Processor Cores}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {933}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261051}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Instruction-Based Delay Fault Self-Testing of Processor Cores SN - 1063-9667 SP EP A1 - Virendra Singh, A1 - Michiko Inoue, A1 - Kewal K Saluja, A1 - Hideo Fujiwara, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Virendra Singh, Nara Institute of Science & Technology, Ikoma, Japan; Central Electronics Engineering Research Institute, Pilani, India

Michiko Inoue, Nara Institute of Science & Technology, Ikoma, Japan

Kewal K Saluja, University of Wisconsin - Madison

Hideo Fujiwara, Nara Institute of Science & Technology, Ikoma, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261051

This paper proposes an efficient methodology of delay fault testing of processor cores using its instruction set. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible. Path delay fault model is used. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan processor is used to demonstrate the effectiveness of our method.

Citation:

Virendra Singh, Michiko Inoue, Kewal K Saluja, Hideo Fujiwara, "Instruction-Based Delay Fault Self-Testing of Processor Cores," vlsid, pp.933, 17th International Conference on VLSI Design, 2004

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