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17th International Conference on VLSI Design
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
Sumit Mediratta, USC Information Sciences Institute
Jeff Sondeen, USC Information Sciences Institute
Jeffrey Draper, USC Information Sciences Institute
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM chips. This paper presents the design of a low area, delay and power router for DIVA. A 58.5% saving in area and 86% reduction in load on the clock as compared to an earlier PIM router design makes the presented design ideal for use in the second version of DIVA, with low area being a critical design requirement for DIVA. This paper also gives a comparison of the presented design with an earlier PIM router design in terms of delay and power to justify the new design choice.
Citation:
Sumit Mediratta, Jeff Sondeen, Jeffrey Draper, "An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System," vlsid, pp.863, 17th International Conference on VLSI Design, 2004
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