Synthesis of Full-Adder Circuit Using Reversible Logic

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Hafiz Hasan Babu, Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury, "Synthesis of Full-Adder Circuit Using Reversible Logic," VLSI Design, International Conference on, pp. 757, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1261020, author = {Hafiz Hasan Babu and Rafiqul Islam and Syed Mostahed Ali Chowdhury and Ahsan Raja Chowdhury}, title = {Synthesis of Full-Adder Circuit Using Reversible Logic}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {757}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261020}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Synthesis of Full-Adder Circuit Using Reversible Logic SN - 1063-9667 SP EP A1 - Hafiz Hasan Babu, A1 - Rafiqul Islam, A1 - Syed Mostahed Ali Chowdhury, A1 - Ahsan Raja Chowdhury, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Hafiz Hasan Babu, University of Dhaka, Bangladesh

Rafiqul Islam, University of Dhaka, Bangladesh

Syed Mostahed Ali Chowdhury, University of Dhaka, Bangladesh

Ahsan Raja Chowdhury, University of Dhaka, Bangladesh

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261020

A reversible gate has the equal number of inputs and outputs and one-to-one mappings between input vectors and output vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states. This correspondence introduces a reversible full-adder circuit that requires only three reversible gates and produces least number of "garbage outputs", that is two. After that, a theorem has been proposed that proves the optimality of the propounded circuit in terms of number of garbage outputs. An efficient algorithm is also introduced in this paper that leads to construct a reversible circuit.

Citation:

Hafiz Hasan Babu, Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury, "Synthesis of Full-Adder Circuit Using Reversible Logic," vlsid, pp.757, 17th International Conference on VLSI Design, 2004

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