Carry Circuitry for LUT-Based FPGA

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Carry Circuitry for LUT-Based FPGA

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	Similar Articles Articles by Varun Jindal Articles by Alpana Agarwal

17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Varun Jindal, Alpana Agarwal, "Carry Circuitry for LUT-Based FPGA," VLSI Design, International Conference on, pp. 731, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1261014, author = {Varun Jindal and Alpana Agarwal}, title = {Carry Circuitry for LUT-Based FPGA}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {731}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261014}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Carry Circuitry for LUT-Based FPGA SN - 1063-9667 SP EP A1 - Varun Jindal, A1 - Alpana Agarwal, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Varun Jindal, Thapar Institute of Engineering and Technology, Patiala, India

Alpana Agarwal, Thapar Institute of Engineering and Technology, Patiala, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261014

This paper presents a carry chain design optimized for implementing multipliers along with the adder circuitry. This kind of architecture will be very useful for designs which have very large number of mathematical operations in it. The aim of the architecture is to accommodate as much logic as possible in one LUT without increasing the size of the LUT proportionately. The discussed carry chain design is compatible with both 3-input as well as 4-input LUTs. The paper ends with a comparative study of multiplier implementation on various popular FPGA architectures.

Citation:

Varun Jindal, Alpana Agarwal, "Carry Circuitry for LUT-Based FPGA," vlsid, pp.731, 17th International Conference on VLSI Design, 2004

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