Sizing Consideration for Leakage Control Transistor

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Sizing Consideration for Leakage Control Transistor

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by F. Farbiz Articles by M. Farazian Articles by M. Emadi Articles by K. Sadeghi

17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	F. Farbiz, M. Farazian, M. Emadi, K. Sadeghi, "Sizing Consideration for Leakage Control Transistor," VLSI Design, International Conference on, pp. 639, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260992, author = {F. Farbiz and M. Farazian and M. Emadi and K. Sadeghi}, title = {Sizing Consideration for Leakage Control Transistor}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {639}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260992}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Sizing Consideration for Leakage Control Transistor SN - 1063-9667 SP EP A1 - F. Farbiz, A1 - M. Farazian, A1 - M. Emadi, A1 - K. Sadeghi, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

F. Farbiz, University of Tehran, Iran

M. Farazian, University of California San Diego

M. Emadi, University of Sharif, Tehran, Iran

K. Sadeghi, University of Sharif, Tehran, Iran

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260992

In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized. The transistor is modeled by a neural network to increase the speed and the accuracy of the calculations.

Citation:

F. Farbiz, M. Farazian, M. Emadi, K. Sadeghi, "Sizing Consideration for Leakage Control Transistor," vlsid, pp.639, 17th International Conference on VLSI Design, 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.