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17th International Conference on VLSI Design
A New Approach To Topology Selection For Cell-Level Analog Circuits
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
ASCII Text
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S. Nagar, B. Mazhari, "A New Approach To Topology Selection For Cell-Level Analog Circuits," VLSI Design, International Conference on, pp. 619, 17th International Conference on VLSI Design, 2004.
 
 
BibTex
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@article{ 10.1109/ICVD.2004.1260987,
author = {S. Nagar and B. Mazhari},
title = {A New Approach To Topology Selection For Cell-Level Analog Circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2004},
issn = {1063-9667},
pages = {619},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260987},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A New Approach To Topology Selection For Cell-Level Analog Circuits
SN - 1063-9667
SP
EP
A1 - S. Nagar,
A1 - B. Mazhari,
PY - 2004
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
S. Nagar, Indian Institute of Technology
B. Mazhari, Indian Institute of Technology
A new approach for selecting a topology from among a fixed set of alternatives for cell-level analog circuits is presented. The topology selection is based on the description of each circuit topology as a set of constraints among the specifications expressed in the form of analytical equations. The proposed topology selection methodology is illustrated using the example of CMOS current sources, voltage amplifiers and differential pair.
Citation:
S. Nagar, B. Mazhari, "A New Approach To Topology Selection For Cell-Level Analog Circuits," vlsid, pp.619, 17th International Conference on VLSI Design, 2004
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