Can SAT be used to Improve Sequential ATPG Methods?

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VLSID
2004
17th International Conference on VLSI Design
Abstract - Can SAT be used to Improve Sequential ATPG Methods?

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17th International Conference on VLSI Design

Can SAT be used to Improve Sequential ATPG Methods? (PDF)

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Mukul R Prasad, Michael S Hsiao, Jawahar Jain, "Can SAT be used to Improve Sequential ATPG Methods?," VLSI Design, International Conference on, pp. 585, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260982, author = {Mukul R Prasad and Michael S Hsiao and Jawahar Jain}, title = {Can SAT be used to Improve Sequential ATPG Methods?}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {585}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260982}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Can SAT be used to Improve Sequential ATPG Methods? SN - 1063-9667 SP EP A1 - Mukul R Prasad, A1 - Michael S Hsiao, A1 - Jawahar Jain, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Mukul R Prasad, Fujitsu Laboratories of America, Sunnyvale, CA

Michael S Hsiao, Virginia Tech, Blacksburg, VA

Jawahar Jain, Fujitsu Laboratories of America, Sunnyvale, CA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260982

In this work we investigate the integration of SAT methods into a simulation-based sequential ATPG tool, STRATEGATE [11], with the aim of improving the state-of-the-art in sequential ATPG. We offer a detailed analysis of possible scenarios and algorithms for performing such an integration. Our preliminary investigations show that such hybrid approaches can be very promising.

Citation:

Mukul R Prasad, Michael S Hsiao, Jawahar Jain, "Can SAT be used to Improve Sequential ATPG Methods?," vlsid, pp.585, 17th International Conference on VLSI Design, 2004

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