The size and complexity of digital systems doubles from one generation to the next. This has made verification a difficult task. In order to build future digital systems designers will need verification tools that are fast and can accommodate large designs. In this paper we present a novel partitioning and control scheme of an emulation system for which the response time, seen by the environment, for the design being emulated can be made independent of the design size. Coupled with the fact that this technique also results in a modular control scheme, this, in principle, promises unlimited scalability.The individual emulation modules operating under this control scheme resemble a particular form of an asynchronous pipeline. We show, using simulations that the throughput performance of this pipeline is dominated by the worst-case behaviour of individual modules (in the same manner as is observed for a normal pipeline). We argue that this pipelined architecture enables the construction of arbitrarily large emulation systems in a natural and structured manner.