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17th International Conference on VLSI Design
System-on-Chip (SoC): Clocking and Synchronization Issues
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
ASCII Text
x 
 
Ramalingam Sridhar, "System-on-Chip (SoC): Clocking and Synchronization Issues," VLSI Design, International Conference on, pp. 520, 17th International Conference on VLSI Design, 2004.
 
 
BibTex
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@article{ 10.1109/ICVD.2004.1260973,
author = {Ramalingam Sridhar},
title = {System-on-Chip (SoC): Clocking and Synchronization Issues},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2004},
issn = {1063-9667},
pages = {520},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260973},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - System-on-Chip (SoC): Clocking and Synchronization Issues
SN - 1063-9667
SP
EP
A1 - Ramalingam Sridhar,
PY - 2004
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Ramalingam Sridhar, University at Buffalo, NY
Technology scaling continues to improve transistor performance and integration to realize complex systems and added functionality in SoC designs. This reduces the energy consumed with a 30% speed improvement per technology generation. The scaling, however, comes with some adverse effects posing perceived barriers.
In this paper, we discuss the design challenges in Ultra Deep Submicron (UDSM) technologies and the scaling problems in SoC circuits for clocking and synchronization. This includes delay variations and functional errors due to various types of noise sources. Correct clocking and synchronization can be achieved through innovative strategies that work at all levels of abstraction.
Citation:
Ramalingam Sridhar, "System-on-Chip (SoC): Clocking and Synchronization Issues," vlsid, pp.520, 17th International Conference on VLSI Design, 2004
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