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17th International Conference on VLSI Design
Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
David D. Wentzloff, Massachusetts Institute of Technology
Benton H. Calhoun, Massachusetts Institute of Technology
Rex Min, Massachusetts Institute of Technology
Alice Wang, Massachusetts Institute of Technology
Nathan Ickes, Massachusetts Institute of Technology
Anantha P. Chandrakasan, Massachusetts Institute of Technology
In order to break the 100 ?W average power barrier of a wireless microsensor node, aggressive design methodologies need to be developed. Dynamic voltage scaling should be more aggressive, reaching subthreshold operation, and knobs should be available for adapting hardware bit-precision and latency. Since the nodes operate in a sleep state most of the time, standby leakage currents must be reduced and the power supply voltage regulated to a near-optimum value. This paper presents insight and simulation/experimental results addressing some of the challenges of designing next generation wireless microsensor nodes.
Citation:
David D. Wentzloff, Benton H. Calhoun, Rex Min, Alice Wang, Nathan Ickes, Anantha P. Chandrakasan, "Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes," vlsid, pp.361, 17th International Conference on VLSI Design, 2004
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