Stacking of "off" transistors has been shown to reduce sub-threshold leakage of the stack. This paper presents an analysis of optimal selection of device widths for such stacked configurations for total leakage reduction. We show that forced stacking always results in an increase in gate leakage if identical performance is desired. We further present an analysis of optimal width ratios for sub-threshold and gate leakage reduction, and derive bounds on the input occurrence probability that ensures total leakage reduction with forced stacking. We demonstrate that leakage is greatly minimized if the stack is optimized for gate leakage rather than for sub-threshold leakage. Finally, we investigate optimization for total leakage and show that as gate leakage becomes dominant, optimization for gate leakage will be identical to total leakage optimization.