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17th International Conference on VLSI Design
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
Rui Min, University of Cincinnati, OH
Zhiyong Xu, University of Cincinnati, OH
Yiming Hu, University of Cincinnati, OH
Wen-ben Jone, University of Cincinnati, OH
We call comparing a small part of two tags a Partial Comparison. In this paper, we show that the partial comparison method can filter out most of the unmatched tag comparisons for different cache configurations. The delay of the partial comparison operation is only 60% of that of the full comparison. This paper proposes to use the partial comparison technique to reduce energy dissipation on major cache components of set-asscociative caches. We show that when adaptive schemes based on partial comparison are applied to amplifiers and bit-lines, the power consumption of set-associative caches is similar to that of direct-mapped caches.
We used the CACTI cache model to evaluate the proposed cache architecture and the Simplescalar CPU simulator to produce final results. The power simulation results suggest that the proposed set-associative cache architecture is very power-efficient. In the simulated cache configurations, 25%-60% of cache accessing engergy was saved.
Citation:
Rui Min, Zhiyong Xu, Yiming Hu, Wen-ben Jone, "Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs," vlsid, pp.183, 17th International Conference on VLSI Design, 2004
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