A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Rasoul Dehghani, "A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer," VLSI Design, International Conference on, pp. 163, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260919, author = {Rasoul Dehghani}, title = {A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {163}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260919}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer SN - 1063-9667 SP EP A1 - Rasoul Dehghani, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Rasoul Dehghani, Sharif University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260919

The design of a fully-integrated \Delta\Sigma-controlled fractional-N frequency synthesizer is described. Using a dual modulus 64/72 prescalar based on injection locking technique and a novel third order digital \Delta\Sigma modulator, we achieved an extremely low power synthesizer in 2.5GHz band.. Total power dissipation of the frequency synthesizer is less than 6mW at a 1.5V supply. The loop bandwidth is optimized to achieve a -123dBc/Hz phase noise at 3MHz offset frequency. The locking time of the loop is less than 30?s.

Citation:

Rasoul Dehghani, "A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer," vlsid, pp.163, 17th International Conference on VLSI Design, 2004

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