Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Anup Savla, Jennifer Leonard, Arun Ravindran, "Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration," VLSI Design, International Conference on, pp. 157, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260918, author = {Anup Savla and Jennifer Leonard and Arun Ravindran}, title = {Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {157}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260918}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration SN - 1063-9667 SP EP A1 - Anup Savla, A1 - Jennifer Leonard, A1 - Arun Ravindran, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Anup Savla, The Ohio State University

Jennifer Leonard, The Ohio State University

Arun Ravindran, University of North Carolina at Charlotte

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260918

This paper presents an ADC architecture which enhances accuracy of pipelines conversion using digital calibration. The popular 1.5 bit/stage pipeline architecture is adapted to an arbitrary radix structure. Calibration algorithms that estimate gain errors for two comparators in each pipeline stage are developed using this architecture. A low-noise queuing technique which enables calibration to be performed in background without interrupting the ADC input sample stream is presented.

A 12-stage pipeline ADC model is used to demonstrate the effectiveness of calibration algorithms. With 10% error in the interstage gain, calibration improves the accuracy from 5 to 11 bits. Effects of implementation issues such as gain parameter settling, intradie gain variation, and finite word length computation are studied.

Citation:

Anup Savla, Jennifer Leonard, Arun Ravindran, "Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration," vlsid, pp.157, 17th International Conference on VLSI Design, 2004

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