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16th International Conference on VLSI Design
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing
New Delhi, India
January 04-January 08
ISBN: 0-7695-1868-0
ASCII Text
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Santanu Chattopadhyay, Naveen Choudhary, "Genetic Algorithm based Approach for Low Power Combinational Circuit Testing," VLSI Design, International Conference on, pp. 552, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183192,
author = {Santanu Chattopadhyay and Naveen Choudhary},
title = {Genetic Algorithm based Approach for Low Power Combinational Circuit Testing},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {552},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183192},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Genetic Algorithm based Approach for Low Power Combinational Circuit Testing
SN - 1063-9667
SP
EP
A1 - Santanu Chattopadhyay,
A1 - Naveen Choudhary,
PY - 2003
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Santanu Chattopadhyay, Indian Institute of Technology
Naveen Choudhary, Indian Institute of Technology
With the advancement in automation, periodic testing of electronic circuits during their lifetime is becoming more and more important. For such a circuit, it is thus very much necessary to reduce the power requirement during the testing phase also. This paper presents a Genetic Algorithm based formulation to solve the problem of generating a test pattern set such that it has high fault coverage and low power consumption. Exhaustive experimentation done on ISCAS85 combinational benchmark suite has shown that the this tool results in upto 78% reduction in transition activity over the original test set generated by ATPGs like ATALANTA [1].
Citation:
Santanu Chattopadhyay, Naveen Choudhary, "Genetic Algorithm based Approach for Low Power Combinational Circuit Testing," vlsid, pp.552, 16th International Conference on VLSI Design, 2003
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