The desired low power and high speed operation of Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits is driving force for CMOS scaling into the Sub-100nm regime. In addition to the supply voltage, the threshold voltage needs to be scaled proportionately for low power operation. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to the problems involved in Sub-100nm device scaling for low power CMOS.This work focuses on the device optimisation for such low power Ultra Large Scale Integrated (ULSI) circuits using a novel implementation of Electrically Induced Junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed dc as well as transient simulation results bring out the advantages of this novel structure.