Due to substantial mixed analog-digital circuit integration in one chip, CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binary-scaled tree-topology power routing has been shown to be critical for minimizing chip area and providing low spatial pattern noise. Imaging artifacts due to timing asymmetry has been quantified, and methods for elimination of the artifacts have been demonstrated. The impact of on-chip bias-generation and drive circuits on the on-chip ADC performance has been shown. New timing and circuit layout techniques has been presented for enabling random noise limited performance of a CMOS imager.